The solution for the multiprocessor system architecture is Application specific Network on Chip (NoC) architectures which are emerging as a leading technology. Modeling and simulation of multilevel network structure and synthesis for custom NoC can beneficial in addressing several requirements such as bandwidth, inter process communication, multitasking application use, deadlock avoidance, router structures and port bandwidth. NoC’s are constructed and their arrangement are done by its topology with the organization of 2D and 3Drouters. The papers focuses on the comparative design and analysis of 2D and 3D network on chip routers for configure mesh topological NoC. The work is carried out in Xilinx 14.2 Software and modules are functionally simulated in latest modelsim 10.0 student edition software. The chip design are tested well on Virtex-5 FPGA and validated in the same hardware by the experimental work.
Volume 11 | 04-Special Issue
Pages: 2573-2581