This paper presents FPGA hardware implementation of circuit under test (CUT) in design for testability (DFT). A three-tap FIR filter is selected and implemented as a CUT using a low-cost test pattern generator (TPG). Full and partial scan design strategies are introduced in this paper. The full scan is proposed to achieve high fault detection efficiency considering minimum possible area overhead for the whole CUT at the same time. While the partial scan individually detects the fault in any part of the CUT. The proposed CUT architecture is implmented in VHDL and tested for area and timing optimization using various set of filter coefficients. Only 61 slices and 109 LUT from the available resources in Spartan 3 FPGA is used to implement the proposed system. The achieved error detection rate for the CUT is up to 100 % with a maximum speed of 479 MHz.
Volume 11 | 01-Special Issue
Pages: 1828-1836