Adders play a key role in the performance of a digital system. The design of an efficient adder has to provide the relation among speed and space that aides in maximizing the system performance. The performance of the adder mainly depends on the delay. Many improvements have been made to improve the performance of the adder architecture by reducing the delay. Most of the adder architectures are proposed with large delay and area. This paper mainly proposes a novel adder architecture using Parallel Prefix Adder (PPA) to reduce the delay. PPA has three stages such as pre-computing stage; carry generation network stage and post-computing stage. The carry of the operation is done in carry generation network stage with less number of gates in the final level. The total architecture of PPA is implemented in transistor level PMOS and NMOS by using tanner tools software. The simulation results shows that the proposed PPA adder architecture provides high speed than existing techniques with less number of gates.
Volume 11 | Issue 5