A Review on Leakage Current & Power Minimization of SRAM Using 10 Transistor

Mohit Kumar Sharma and Kanchan Sengar

This paper provide a method for designing a power efficient SRAM cell. The cell works efficiently on low power dissipation because of its series-connected tail transistor and arrangements read buffers, which provide a stacking effect in the given design. This paper also provides the impact of process, voltage, and temperature (PVT) variations on most of the design metrics of the SRAM cell and show the tabular differences with other designs of SRAM cells.

Volume 11 | 07-Special Issue

Pages: 33-40