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Nanocell Parity Generator (PG) Circuits Design and Power Dissipation Analysis


A. Mallaiah, G.N. Swamy and K. Padmapriya
Abstract

Quantum-dot cellular automata (QCA) is one of the rising advancement and ITRS report gives a decent outline of future advancements. Since it was first presented in 1993, test devices for semiconductor, atomic, and attractive methodologies have been created. Late papers demonstrate that QCA can accomplish extreme density, quick exchanging speed, and room temperature work. The key QCA cell uses to construct binary logic gates, logic wires, and both combinational and sequential circuits. Even Parity bit generator (PG) circuit for 4, 8, 16 and 32-bit circuits introduced in this paper with QCA technology. The proposed QCA layouts are better to compare to the past best structure regarding various cells, viable region, and clock latency. Proposed 4 bit PG 66.66% less number of cells taken 40% less area, 57.14% of clock latency compare recent design, also verified the 8, 16 and 32 bit PG circuits. QCA Designer 2.0.3 is used to simulating these circuits and QCA Probabilistic (QCAPro) software is used to find the total energy dissipation.

Volume 11 | 07-Special Issue

Pages: 139-144