Multipliers are one amongst the fundamental logic circuits which are used widely in almost each and every computing device. Improvising the speed and reducing the power consumption of multiplier will positively impact the current computational industry by virtue of its popularity. An Error Detectable Multiplier Circuit using CNFET Technology is proposed in this paper. The proposed design has been simulated using 32 nm CNFET Technology at a supply voltage (VDD) of +0.9 V with the help of Cadence Virtuoso CAD tool. Power, delay and power-delay product (PDP) are the parameters considered here for the evaluation of the performance of the proposed circuit.
Volume 11 | 07-Special Issue
Pages: 150-156