The multiplier is one of the msost important key hardware blocks in most digital and high-performance systems, such as digital signal processors and microprocessors. Wallace Tree Multiplier provides a power-efficient approach for high-speed multiplication. Now, we using a novel (15,4) Binary counter using Symmetric Stacking for the reduces the Counter based Wallace Tree (CBT) Multiplier can be improve the multiplier speed. A novel 15:4 binary counter is proposed by using (7,3) counter and proposed Full Adder based circuit.
Volume 11 | Issue 5