This paper presents Reconfigurable FIR (RFIR) Filter design based on Adaptive Distributed Arithmetic (ADA) for high performance and high throughput. The intricacies of computation and design of RFIR filters are reduced by multiplier less method DA which uses RAM and RAM based Look Up Tables (LUTs). For the ASIC realization, RAM and RAM based LUTs proved as very expensive. To overcome this problem this paper presents LUT design which is purely based on Register. The Register based LUT design exploits maximal sharing of results obtained during Partial Product Generation. Also, it has been presented that utilization of Inter Iterative Shared (IIS) LUT and Speculative Adders integration in DA mechanism reduces Power Consumption, Area, Delay and complexity of design and remarkably improves the Speed. Integrating Speculative Adders in DA tree structures exploit the reduction in Area – Delay Product [ADP]. The proposed design nearly has 50%, 45% and 65% area-delay product and 60%, 55% and 60% less power consumption than conventional DA based Systolic Structure, traditional DA based shared LUT and Carry Save Adders [CSA] structures respectively. Further the same architecture has been implemented in Programmable Field Programmable Gate Arrays (PFPGA) of Xilinxxc7s25csga324-1IL and offers nearly 45% reduction of utilization of resources when it is compared with the existing structures.
Volume 11 | 07-Special Issue
Pages: 296-302