In modern digital world requirements for a highly efficient low power Software defined radios (SDR) are in demand since the evolution of advanced digital gadgets. Fast Fourier Transform (FFT) is the major building block of SDR architecture. FFT architecture consists of multipliers, block Random Access Memory (RAM) and Read Only Memory (ROM) memories for storing predefined widdle factors and intermediate stage results while processing. Clock gating approach for limiting the switching activities of the FFT computational units are discussed in this paper.FFT operation requires sequence memory accessing so a ring counter can be substituted instead of an address decoder. A pre clock predicting C- element is utilized to control the clock tree architecture to isolate the ideal counter blocks of the ring counter. A Gated driver tree is further employed to control the loading time of the FFT memory blocks. Atypical 8-point FFT architecture with adaptive clock gating and data driver trees are designed and implemented in Hardware Description Language (HDL)modeling and tested with Cyclone II FPGA platform. The presented clock gated FFT architecture results in 50 % power reduction than the conventional FFTs.
Volume 11 | 01-Special Issue
Pages: 846-853