Memory is the elementary and essential part in most of embedded portable devices. Over which the SRAM memory is most widely used memory in embedded applications. In modern VLSI design, the optimization of any logical circuit is a significant metric. The optimization factor in terms of low power dissipation and adequate throughput rate is required. Power dissipation is an important issue due to proliferation of portable Electronic devic-es. Battery life is determined by consumption of energy per task. Reduction of power done at different level of ab-straction in VLSI design, over which the power dissipation in circuit level of abstraction gives better system throughput than other level of abstraction. The phenomenal development of reducing the power would gain impor-tance with developments of nanometer Technologies. The proposed design using 8T SRAM circuit is implemented and analyzed in circuit level, array level and row column based memory architecture level. The 8T SRAM circuit decreases the sub threshold leakage current by reducing the flipping of states in SRAM circuit. Introducing the two PMOS in proposed design reduces the momentary unwanted switching transient at a logic function (i.e ., glitch).To execute the proposed design,90nm technology, Digital Schematic and micro wind software is used.
Volume 11 | 01-Special Issue
Pages: 1130-1135