Memory Design Using by Multibit Flip Flop

Devi, Dr.K.P. Kaliyamurthie and S. Srigowtham

Power optimization is one of the most important factor in memory devices. Because the power consumption of the memory device increases means, the device reliability and life time is reduced. By using the array of flip-flops the Static Random Access Memory (SRAM) is designed. The clock network of the flip-flop consumes more power. To reduce this clock power, the Single-Bit Flip-Flop (SBFF) is replaced by Multi-Bit Flip-Flop (MBFF). The Multi-Bit Flip-Flop does not reduce the number of flip-flops; it only reduces the number of inverters in clock networks. So the power consumption of the flip-flop is reduced. While designing the memory by using SBFF means it consumes more power. So MBFF is used to design the memory. The general type of SRAM performs a single operation (Read or Write) in each clock pulse, depending on its Read/Write control signal. To overcome the disadvantage of general SRAM is designed to perform simultaneous Read and Write operation, because it has separate Read/Write ports. It has many real time applications like high speed communications, military applications, etc. In my project SRAM is designed by using Multi-Bit Flip-Flop

Volume 11 | Issue 4

Pages: 57-61