In the SoC quantity, validation is most vital part in chip manufacturing and in the testing. Verification contributes with definite execution and functionality of DUT (Design under Test) and check that the exact designations meet or not. In this paper, the AHB-LITE Protocol is validated according to the model listing. Assertion Based Verification (ABV) is most commonly used validation technique to build up the validation standard and minimizing the debugging time of complicated design and also ease the validate process. Coverages are used to check the exact functionality specifications meet or not. Initially the architecture of AHB Lite model is designed using single master-multiple slaves in verilog language and simulates the design using MODELSIM tool and the protocol is validated with the assertions and coverages technique i.e. done in QUESTASIM tool. The model is integrated and appliance in XILINX ISE tool. In this synthesize will be done for the respective design based on the stipulation. So that observed the timing analysis for the respective design.
Volume 11 | 09-Special Issue
Pages: 305-312
DOI: 10.5373/JARDCS/V11/20192572