Power Efficient Router Framework for Wireless Network on Chip (WNoC)

Dr.J. Kalaivani and Dr.B. Vinayagasundaram

In Wireless Networks-on-Chip (WNoC), during routing, it will be difficult to accurately estimate the utilization of downstream routers based on the queue length. Also the threshold value should be updated based on the bandwidth requirements of wireless interface. In this paper, power efficient routing framework is proposed. In this technique, the consumption of bottom wise routers are predicted. During routing, Non-jamming bypass channel (NJBC) is applied to bypass the power reduced routers based on high forward probability. Experimental results proved that developed framework reduces power consumption and increases the transmission efficiency.

Volume 12 | Issue 3

Pages: 119-125

DOI: 10.5373/JARDCS/V12I3/20201173