In this paper, we propose an N-bit Kogge-Stone Adder for low power and high speed arithmetic. Kogge-Stone Adder (KSA) is a type of parallel prefix carry look ahead adder (CLA). In O (logn) time carry is generated in this adder and it is a fastest adder which is considered widely in industry for producing high performance arithmetic circuits. In KSA, parallel computation is used for generating carry in quick manner at the cost of increased area. A high-speed n-bit Kogge-Stone adder (KSA) has been implemented. The adders are designed using Verilog and synthesized using front-end tool including analysis for performance, power, and area. Improving the speed of the n-bit (4, 8, 16, 32, 64,128bits….) Kogge-Stone adder with the single module by using GENERATE concept .Optimizing speed of an n-bit KSA without any dynamic power dissipation using the GENERATE concept. Thus increases overall speed of an ALU. Once detecting the particular approaches for input, output, main block and different modules, the Verilog descriptions are run through a Xilinx ISE 10.1 simulator, followed by the timing analysis for validation, functionality and performance of the designated design.
Volume 12 | 04-Special Issue
Pages: 690-696
DOI: 10.5373/JARDCS/V12SP4/20201535