An Improved Code Compression Technique for Embedded Systems Using Optimal Separated Dictionaries

Adepu Shravan Kumar and Dr.S. Srinivasan

Now days the usage of the technology is incrementing day by day. In this present situation the improvement of the technology without any kind of external power sources and the cost should be in the limited and the memory or the size should not be compressed. In the embedding systems the code compression is very important, to transfer the data with the low memory size. For this we need a modified version of Dictionary. It is based on new technique called Bit-Mask. It records the mismatch values and the grater values and their positions of the syntax and then it compresses the greater values and the number of the instructions. For the decoding it refers the exclusive with code words. In this paper we are introducing a small new dictionary, to reduce the high frequency instructions by using the new algorithm Bit-Mask. The advanced Dictionary is assorted by an algorithm was planned to enhance the instruction equal rates. And this algorithm will not affect the compression ratio of the code word. And it increases the separated dictionary performance of the code-word. Contingent upon those test results, the suggested technique can attain a 7. 5% modifying in the layering proportion. The suggested architecture designs of this manuscript dissection that logic size, consumption of power, &area with the use of Xilinx 14.2.

Volume 11 | Issue 11

Pages: 48-54

DOI: 10.5373/JARDCS/V11I11/20193167