A Parametric DFT Scheme for RAMs

Bhogadi Anil Kumar, Chillapalli Haritha, Gumpena Veda Sri Leela, E Raghuveera, K Hari Kishore

Power consumption and Power dissipation plays a major role in the design of the circuit. In this paper we are going to implement a Latch circuit of DFT cell with different logics i.e., CMOS logic, Pass transistor logic and Transmission gate logic and from the design of the cell with different logics we calculate the power dissipation of the circuit. The calculations and the design of the circuit is done using Mentor graphics tool. We have used 130nm technology for the design of the circuit. The circuit which gives the less power dissipation is preferred to design the DFT cell.

Volume 12 | Issue 2

Pages: 2298-2305

DOI: 10.5373/JARDCS/V12I2/S20201275