Novel approach to Design and Implementation of Efficient Multiplier Using Urdhva Triyakbhyam Sutra

K. Rani Rudrama, V.Sireesha, V. Bhanu Prasad, T.Lavanya, P. Naga Jyothi

Multiplier is a significant practical square of a chip since duplication is should have been performed more than once in practically all logical figuring’s and being the key parts of Arithmetic and rational units, Digital sign preparing squares and Multiplier and aggregate units, decide the presentation and throughput of the various applications. Along these lines, for simple increase process Vedic multiplier is presented right now. Vedic Mathematics is an old type of science recreated from the antiquated Indian sacred texts alluded to as Vedas. Vedic Mathematics depends on 16 sutras which execute various parts of science like polynomial math, geometry, arithmetic. Urdhva Triyakbhyam is the most summed up sutra for usage of Vedic Multiplier structure. Urdhva Triyakbhyam implies vertically and diagonally. This paper depicts a plan of 8-bits multiplier design using different adders which is actualized utilizing Urdhva-triyakbhyam sutra of Vedic strategy for multiplication. The multiplier is planned utilizing Xilinx ISE structure suite 14.7 and incorporated on the Spartan3E FPGA board. Comparing of various adders has been thought about.

Volume 12 | Issue 2

Pages: 655-660

DOI: 10.5373/JARDCS/V12I2/S20201037