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Novel Low Power Data Retention Regulating Mechanism Using Dr-Vdr In SRAM Design


M.Damodhar Rao, Y.V. Narayana, V.V.K.D.V. Prasad
Abstract

A dual-rail data-retention-power and voltage regulating systems are in high demand for advanced low-power VLSI systems. The power leakage and de-modernization isa significant problem in VLSI technology, particularly in chip design like Static random access memory (SRAM).The utilization of conventional methods reduces power consumptions but have limitations. It is proposed to use Dual rail-voltage data retention (DR-VDR) cell in addition to power supply unit, adaptive data loss identifier block, active regulating controller and automatic switches in the design of SRAM. The DR-VDR cells consist of a dual-rail circuit with a memory unit, a reset forward signal generating unit and suppressing control circuit which improves the reduction of leakage power up to 96%.In this paper, all designs are implemented with 45nm technology, proposed DR-VDR method comparison with conventional methods is done andconcludes that the proposed method is the best technique for data retention in SRAM design.

Volume 12 | Issue 2

Pages: 823-834

DOI: 10.5373/JARDCS/V12I2/S20201102