Design of Low-Power and Optimized Pseudo Random Sequence Generator Using Gate Diffusion Input (GDI) Technique

Fazal Noorbasha, P. Raga Sai Nikhila, K. Vishnu Teja, K Hari Kishore

In an integrated chip manufacturing technology, reducing the size of chip plays an important role for power dissipation. Low power testing has become an important issue as power dissipation during testing mode is very high as compare to normal mode. LFSR is utilized in testing of ASIC chips by producing pseudo irregular examples. This paper manages structure of low power LFSR by utilizing GDI system. GDI system is one of the low power procedure utilized for actualizing different computerized circuits. This strategy utilizes just two transistors to configuration quick and low power circuits with progress in control attributes. LFSR has been executed by regular and GDI strategy in mentor graphics at 130nm innovation. Relative investigation is completed between the two strategies indicating up to 45.4 % and 20 % decrease in power and zone individually in GDI strategy. Simulation and variation of power with frequency and voltage is also discussed.

Volume 12 | Issue 2

Pages: 1204-1210

DOI: 10.5373/JARDCS/V12I2/S20201155