Analysis of Voltage Stress in Reduced Switch Count of 7 Levels Multilevel Inverter

Nanajee Karri, A.Pandian

In the power conversion technology multilevel inverters are very bright technology among the existing technologies. It provides the stair case wave shape output voltage from constant multiple DC sources which has nearly sinusoidal wave shape. The importance of reduced switch count has merits in modular structure in decreasing the size. As the cascaded H-bridge topology got more attention in the high power medium voltage applications, those topologies are being used extensively. But, increasing of switch count with increase in levels is the only drawback of cascaded H-bridge multilevel inverters. Therefore, in this paper a reduced switch count topology is analyzed for seven level voltages and the analysis of voltage stress is also done. The voltage stress analysis gives the required voltage rating of each switch in the circuit. The work is implemented out by using MATLAB-SIMULINK software and the results are discussed.

Volume 12 | Issue 2

Pages: 1261-1271

DOI: 10.5373/JARDCS/V12I2/S20201162