A 45nm CMOS Power Amplifier with Reconfigurable Gain and Improved Linearity

M.Saritha, Dr. M.Janaki Rani , Dr.M.Anand

Power Amplifier is one of the important circuit that is used to amplify the signal to high output power level. The major challenge in the design of power amplifier is to achieve the linearity when the device has variable gain. In this research, a Cross Coupled Pull Down Network (CCPDN) based power amplifier is designed for achieving the optimum linearity, even when the gain is high or low. The proposed power amplifier has two different stages namely reconfigurable gain stage and power stage. The CCPDN is utilized in the circuitry of reconfigurable gain stage to achieve both the linearity and gain as well as the power stage used to amplify the signal through the PA. The CCPDN based power amplifier is implemented in Generic Process Digital Kit 45 nm(GPDK45nm) technology. The performance of the PA is analyzed in terms of average power, total noise, linearity and stability factor. The performances are compared with an existing power amplifier architecture that is without CCPDN. The average power of proposed power amplifier for mode 1 is 135μW which is less when compared to the power amplifier without CCPDN. Additionally, the designed CCPDN based power amplifier is operated in the range of 2- 2.4 GHz.

Volume 12 | Issue 6

Pages: 387-396

DOI: 10.5373/JARDCS/V12I6/S20201041