Efficient Charge Recovery Adiabatic Logic Design and Implementation of a Novel 32-bit Vedic Multiplier for DSP Applications

T.Suguna,M.Janaki Rani,M.Anand

Portable digital processing systems that perform high computational operations in real-time mainly depend on the performance of multipliers. The reason is that the multiplier unit resides in the critical path and has a direct impact on the power consumption, area, speed, and throughput of the system. Thus fast and an energyefficient multiplier is always needed in the VLSI industry which contributes significantly to high performance and low power consumption of the system. Adiabatic logic is considered as the promising technique in recent years to reduce the power consumption in the VLSI circuits, using Vedic mathematics approach a novel multiplier scheme along with adiabatic logic is proposed in this paper. The adiabatic logic style used for this work is Efficient Charge Recovery logic (ECRL) adiabatic logic, because of its simple and feasible structure. The proposed 32-bit multiplier is implemented using the TANNER tool, at 22 nm technologies and compared with CMOS and GDI logic Vedic multiplier. Parameters like power, area, and delay are nored and comparisons for the different supply voltages and temperatures at 1000 MHz operating frequency are presented and discussed in this paper. It is observed from the results, that the proposed novel multiplier has 49% and 70% less PDP at the supply voltage of 1.5V and 45% and 71% less PDP at 300C temperature than GDI and conventional Vedic multiplier respectively for the mentioned operating frequency. Thus, the proposed novel 32-bit ECRL adiabatic Vedic multiplier can be selected for implementation of efficient high MAC unit and also in the realization of digital IIR and FIR filter that is used in different DSP applications.

Volume 12 | Issue 6

Pages: 1709-1722

DOI: 10.5373/JARDCS/V12I2/S20201370