In the past few years SoC (system on chip) encountered many problems such as power and area reduction for low design cost and better performance. Among various components on the chip, memory parts occupy nearly 50% of chip area and power. These include memory arrays, caches, flip flops, pulsed latches. Pulsed latches have been proposed as efficient replacement of flip flops because they can achieve high performance taking the advantage of both latch and flip flop features. Here a new design to the pulsed latches that has high performance, low power, and low area at different temperature variations is proposed. Circuit is implemented in Cadence gpdk 90 nm technology.
Volume 11 | 03-Special Issue
Pages: 1421-1430