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Design of Conditional Boosting Flip flop in Nano meter Technology


Y. Sandeep and Dr.S. Govindarajulu
Abstract

For low voltage applications where the supply voltage is equal to the near threshold voltage a Conditional Boosting flip flop is proposed. In this paper we are designing the conditional boosting flip flop and we are comparing the proposed flip flop with some conventional flip flop like ACFF, SAFF, CFF. We are designing the proposed flip flop and conventional flip flops in cadence 6.1.6 in 180nm technology. We are calculating power, delay for proposed flip flop and conventional flip flops and the proposed flip flop is providing low power and low delay compared with the conventional flip flops.

Volume 11 | 03-Special Issue

Pages: 1609-1616